View NCP5215MNR2G_4112834.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2008 october, 2008 ? rev. 5 1 publication order number: ncp5215/d ncp5215 dual synchronous buck controller for notebook power system the ncp5215, a high ? efficiency and fast ? transient ? response dual ? channel buck controller, provides a multifunctional power solution for notebook power system. 180 o interleaved operation function between the two channels has capabilities of reducing the common input capacitor requirement and improving noise immunity. adaptive ? voltage ? positioning (avp) control reduces the requirement of output filter capacitors. programmable power ? saving operation ensures high efficiency over entire load range. input feedforward voltage ? mode control is employed to deal with wide input voltage range. transient ? response ? enhancement (tre) control for the both channels enables fast transient response. features ? wide input voltage range: 4.5 v to 24 v ? adjustable output voltage range: 0.8 v to 3.0 v ? selectable nominal fixed switching frequency: 200 khz, 300 khz, and 400 khz ? 180 interleaved operation function between the two channels ? programmable adaptive ? voltage ? positioning (avp) operation ? programmable transient ? response ? enhancement (tre) control ? power saving operation under light load condition ? input feedforward voltage mode control ? resistive or inductor?s dcr current sensing ? 1% internal 0.8 v reference ? external soft ? start operation ? output discharge and soft ? stop ? built ? in gate drivers ? input supplies undervoltage lockout ? output overvoltage and undervoltage protections ? accurate overcurrent protection ? thermal shutdown protection ? qfn40 package ? this is a pb ? free device typical applications ? notebook computers ? cpu chipset power supplies qfn40 mn suffix case 488ar device package shipping ordering information NCP5215MNR2G qfn40 (pb ? free) 2500/t ape & reel http://onsemi.com marking diagram a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package 40 1 ncp5215 awlyywwg fset vcc agnd vref pgood1 pgood2 en1 en2 ss1 ss2 bst1 vccp1 bg1 pgnd1 vin fpwm# pgnd2 bg2 vccp2 bst2 ncp5215 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 treset2 comp2 inv2 fb2 vdrp2 ilim2 cs2 ? /vo2 cs2+ swn2 tg2 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 33 32 31 treset1 comp1 inv1 fb1 vdrp1 ilmt1 cs1 ? /vo1 cs1+ swn1 tg1 (top view) pin connections ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d.
ncp5215 http://onsemi.com 2 figure 1. internal block diagram and typical application 31 tg1 30 bst1 32 swn1 28 bg1 29 vccp1 27 pgnd1 33 34 gate driver 1 pwm1 cs1+ cs1 ? vo1 38 inv1 39 comp1 36 vdrp1 vcc 5vcc protection and control logic 5 pgood1 7 en1 vin 5vcc ncp5215 thermal shutdown vcc vin en_drv1 en_drv2 tsd cdiff1 vref 5vcc 25 fpwm cs1+ cs1 ? /vo1 40 treset1 osc digital counter & 180 o phase shift fb1 37 fb1 6 pgood2 swn1 soft start 1 vo1 26 vin 2 3 agnd vin 1 fset 4 vref oc1 en1 lsen1 ovp1 ovp2 ramp generator & pwm logic 1 fb2 oc2 en2 pgood1 pgood2 vin 5vcc 20 tg2 21 bst2 19 swn2 23 bg2 22 vccp2 24 pgnd2 cs2+ cs2 ? vo2 vin 5vcc 5vcc 0.8v vref over current detector 1 oc1 cdiff1 35 ilim1 9 ss1 dsch1 12 ohm dsch1 dsch2 vref vin clk fpwm ccm1 tre1 comp1 fb1 clk1 vref pwm2 swn2 lsen2 ramp generator & pwm logic 2 gate driver 2 vin clk fpwm clk2 18 17 13 inv2 12 comp2 15 vdrp2 8 en2 cdiff2 cs2+ cs2 ? /vo2 11 treset2 14 fb2 soft start 2 vo2 vref over current detector 2 oc2 cdiff2 16 ilim2 10 ss2 dsch2 12 ohm vref ccm2 tre2 comp2 fb2 vref
ncp5215 http://onsemi.com 3 pin function description pin no. symbol description 1 fset frequency set programmable pin of switching frequency for two channels. 2 vcc vcc this pin powers the control section of ic. 3 agnd analog ground low noise ground for control section of ic. 4 vref reference voltage output internal 0.8 v reference output. 5 pgood1 power good 1 power good indicator of the output voltage of channel 1. (open drained) 6 pgood2 power good 2 power good indicator of the output voltage of channel 2. (open drained) 7 en1 enable 1 enable logic input of channel 1. 8 en2 enable 2 enable logic input of channel 2. 9 ss1 soft ? start 1 soft ? starting programmable pin of channel 1. 10 ss2 soft start 2 soft ? starting programmable pin of channel 2. 11 treset2 transient response enhancement set 2 channel 2 transient ? response ? enhancement (tre) programmable pin. 12 comp2 comp2 output of the error amplifier of channel 2. 13 inv2 inverting input 2 error amplifier?s inverting input pin of channel 2. 14 fb2 feedback 2 output voltage feedback of channel 2. 15 vdrp2 voltage droop 2 channel 2 voltage droop output to the compensation. this pin is used to program the adaptive ? voltage ? position (avp) function for channel 2. 16 ilmt2 current limit 2 current limit programmable pin of channel 2. 17 cs2 ? / vo2 current sense 2 ? channel 2 inductor current differential sense inverting input. 18 cs2+ current sense 2+ channel 2 inductor current differential sense non ? inverting input. 19 swn2 switch node 2 switch node between the top mosfet and bottom mosfet of channel 2. 20 tg2 top gate 2 gate driver output of the top n ? channel mosfet for channel 2. 21 bst2 bootstrap connection 2 channel 2 top gate driver input supply, a bootstrap capacitor connection between swn2 and this pin. 22 vccp2 vcc power 2 this pin powers the bottom gate driver of channel 2. 23 bg2 bottom gate 2 gate driver output of the bottom n ? channel mosfet for channel 2. 24 pgnd2 power ground 2 ground reference and high ? current return path for the bottom gate driver of channel 2. 25 fpwm# forced pwm forced pwm enable logic input. low to enable forced pwm mode and disable power ? saving mode for both channels. 26 vin vin input voltage monitor input. 27 pgnd1 power ground 1 ground reference and high ? current return path for the bottom gate driver of channel 1. 28 bg1 bottom gate 1 gate driver output of the bottom n ? channel mosfet for channel 1. 29 vccp1 vcc power 1 this pin powers the bottom gate driver of channel 1. 30 bst1 bootstrap connection 1 channel 1 top gate driver input supply, a bootstrap capacitor connection between swn1 and this pin. 31 tg1 top gate 1 gate driver output of the top n ? channel mosfet for channel 1. 32 swn1 switch node 1 switch node between the top mosfet and bottom mosfet of channel 1. 33 cs1+ current sense 1+ channel 1 inductor current differential sense non ? inverting input. 34 cs1 ? / vo1 current sense 1 ? channel 1 inductor current differential sense inverting input. 35 ilmt1 current limit 1 current limit programmable pin of channel 1. 36 vdrp1 voltage droop 1 channel 1 voltage droop output to the compensation. this pin is used to program the adaptive ? voltage ? position (avp) function for channel 1. 37 fb1 feedback 1 output voltage feedback of channel 1. 38 inv1 inverting input 1 error amplifier?s inverting input pin of channel 1. 39 comp1 comp1 output of the error amplifier of channel 1. 40 treset1 transient response enhancement set 1 channel 1 transient ? response ? enhancement (tre) program pin.
ncp5215 http://onsemi.com 4 maximum ratings rating symbol value unit power supply voltages to agnd v cc , v ccp1 , v ccp2 ? 0.3, 6.0 v high ? side gate driver supplies: bst1 to swn1, bst2 to swn2 high ? side fet gate driver voltages: tg1 to swn1, tg2 to swn2 v bst1 ? v swn1 , v bst2 ? v swn2 , v tg1 ? v swn1 , v tg2 ? v swn2 , ? 0.3, 6.0 v input voltage sense inputs to agnd v in ? 0.3, 27 v switch nodes v swn1 , v swn2 ? 4.0 (<100 ns), ? 0.3 (dc), 32 v pgnd1, pgnd2 to agnd v gnd ? 0.3, 0.3 v thermal characteristics thermal resistance, junction ? to ? air (pad soldered to pcb) r ja 36 c/w operating junction temperature range t j ? 40 to +150 c operating ambient temperature range t a ? 40 to +85 c storage temperature range t stg ? 55 to +150 c moisture sensitivity level msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device contains esd protection and exceeds the following tests: human body model (hbm) 2.0kv per jedec standard: jesd22 ? a114. machine model (mm) = 200v per jedec standard: jesd22 ? a115, except pin 17 and pin 34, which are 150v. 2. latchup current maximum rating: 150ma per jedec standard: jesd78.
ncp5215 http://onsemi.com 5 electrical characteristics (v cc = 5.0 v, v in = 12 v, f set = 5.0 v, fsw = 300 khz, t a = ? 40 c to 85 c, unless otherwise noted.) characteristic symbol test conditions min typ max unit supply voltage input v oltage vin ? 4.5 ? 24 v v cc operating v oltage v cc ? 4.5 5.0 5.5 v v ccp1 operating v oltage v ccp1 ? 4.5 5.0 5.5 v v ccp2 operating v oltage v ccp2 ? 4.5 5.0 5.5 v supply current v cc quiescent supply current in normal operation i vcc_n ven1 = ven2 = 5.0 v, vfpwm# = 0 v tg1, bg1, tg2, and bg2 are open ? 3.0 6.0 ma v cc quiescent supply current in power ? saving operation i vcc_ps ven1 = ven2 = 5.0 v, vfpwm# = 5.0 v tg1, bg1, tg2, and bg2 are open ? 3.0 6.0 ma v cc shutdown current i vcc_sd ven1 = ven2 = 0 v ? ? 10 a v ccp quiescent supply current in normal operation i vccp1_n , i vccp2_n ven1 = ven2 = 5.0 v, vfpwm# = 0 v tg1, bg1, tg2, and bg2 are open ? 1.2 2.0 ma v ccp shutdown current i vccp1_sd , i vccp2_sd ven1 = ven2 = 0 v ? ? 10 a bst quiescent supply current in normal operation i bst1_n , i bst2_n ven1 = ven2 = 5.0 v, vfpwm# = 0 v tg1, bg1, tg2, and bg2 are open ? 1.0 2.0 ma bst shutdown current i bst1_sd , i bst2_sd ven1 = ven2 = 0 v ? ? 5.0 a voltage ? monitor v cc start threshold vcc uv+ v cc and v ccp are connected to the same voltage source 4.05 4.25 4.48 v v cc uvlo hysteresis vcc hys ? 200 275 400 mv power good higher threshold vpgh with respect to error comparator threshold of 0.8 v ? 112 ? % power good lower threshold vpgl with respect to error comparator threshold of 0.8 v ? 88 ? % output overvoltage trip threshold fbovpth with respect to error comparator threshold of 0.8 v 113 117 121 % overvoltage fault propagation delay ? fb forced 2% above trip threshold ? 1.5 ? s output undervoltage trip threshold fbuvpth with respect to error comparator threshold of 0.8 v 63 68 73 % output undervoltage protection blanking time uvpt blk (note 3) ? 16/fsw ? s vref output reference v oltage v ref t a = 25 c t a = ? 40 to 85 c 0.796 0.792 0.8 ? 0.804 0.808 v reference load regulation v ref ivref = 0 to 100 a ? ? 4.0 mv sinking current isink_vref vref rises 10% 20 ? ? a current limit current limit threshold v ((cs+) ? (cs ? )) v ilim = 0.4 v 72 80 88 mv ilim setting range range ilim (note 3) ? ? 0.8 v 3. guaranteed by design, not tested in production.
ncp5215 http://onsemi.com 6 electrical characteristics (continued) (v cc = 5.0 v, v in = 12 v, f set = 5.0 v, fsw = 300 khz, t a = ? 40 c to 85 c, unless otherwise noted) characteristic symbol test conditions min typ max unit thermal shutdown thermal shutdown ts d (note 4) ? 150 ? c thermal shutdown hysteresis tsdhys (note 4) ? 30 ? c oscillator operation frequency fsw fset pin open loop (t a = 25 c) 160 200 240 khz pull high fset pin (t a = 25 c) (t a = ? 40 c to 85 c) 262.5 255 300 ? 337.5 345 khz pull low fset pin (t a = 25 c) 340 400 460 khz soft ? start soft ? start source current i ss ? 3.0 4.0 5.0 a soft ? start complete threshold v ssth (note 4) ? 0.9 ? v switching regulators main ramp amplitude v oltage vramp v in = 5.0 v (note 4) ? 1.25 ? v maximum duty cycle dmax v in = 5.0 v ? 92 ? % v in = 12 v ? 48 ? % v in = 24 v ? 27 ? % gate drivers tg gate pull ? high resistance r h_tg1 , r h_tg2 v bst ? v swn = 5.0 v, v tg ? v swn = 4.0 v ? 1.5 4.0 tg gate pull ? low resistance r l_tg1 , r l_tg2 v bst ? v swn = 5.0 v, v tg ? v swn = 1.0 v ? 1.5 4.0 bg gate pull ? high resistance r h_bg1 , r h_bg2 v ccp = 5.0 v, v bg = 4.0 v ? 1.5 4.0 bg gate pull ? low resistance r l_bg1 , r l_bg2 v ccp = 5.0 v, v bg = 1.0 v ? 0.5 1.5 dead time t lh bg falling to tg rising ? 42 ? ns t hl tg falling to bg rising ? 34 ? differential current error amplifier input bias current cs ? iib ? ? 200 ? 200 na cs+ to cs ? input signal range vcs_max refer to agnd ? ? 3.0 v output voltage swing vos_drp (note 4) 0.6 ? 1.0 v offset current at vdrp ioffset_drp (cs+) ? (cs ? ) = 0 v, no connection from vdrp pin to vref ? 1.0 ? 1.0 a [(cs+) ? (cs ? )] to vdrp gain gain_cs ((v_vdrp ? vref)/ ((cs+) ? (cs ? ))) (cs+) ? (cs ? ) = 20 mv 2.35 2.6 2.85 v/v internal droop resistance r drp from v drp to v ref 2.4 2.65 2.9 k 4. guaranteed by design, not tested in production.
ncp5215 http://onsemi.com 7 electrical characteristics (continued) (v cc = 5.0 v, v in = 12 v, f set = 5.0 v, fsw = 300 khz, t a = ? 40 c to 85 c, unless otherwise noted) characteristic symbol test conditions min typ max unit voltage error amplifier dc gain gain_vea (note 5) ? 80 ? db unity gain bandwidth ft_vea (note 5) ? 13 ? mhz slew rate sr_vea (note 5) (comp pin to gnd = 100 pf) ? 1.0 ? v/ s inverting input current i inv1 , i inv2 v inv = 0.8 v ? ? 0.5 a output voltage swing vos_ea ? 1.0 ? 3.0 v source current isource_ea comp = 3.0 v 2.0 4.0 ? ma sink current isink_ea comp = 1.0 v 1.5 2.0 ? ma control section ven1, ven2 threshold high v en1_h , v en2_h ? 1.4 ? ? v ven1, ven2 threshold low v en1_l , v en2_l ? ? ? 0.5 v ven1, ven2 source current i en1_source , i en2_source ? ? ? 0.5 a ven1, ven2 sink current i en1_sink , i en2_sink ? ? ? 0.5 a vfpwm# threshold high v fpwm_h ? 1.4 ? ? v vfpwm# threshold low v fpwm_l ? ? ? 0.5 v vfpwm# source current i fpwm_source ? ? ? 0.5 a vfpwm# sink current i fpwm_sink ? ? ? 0.5 a pgood pin on resistance pgood_r i_pgood = 5.0 ma ? 25 ? pgood pin off current pgood_lk ? ? ? 1.0 a output discharge mode output discharge on ? resistance r discharge ? ? 12 ? system restart threshold of the output voltage vth_srst ? 0.2 0.3 0.4 v tre offset treset offset current i tre ? 3.0 4.0 5.0 a 5. guaranteed by design, not tested in production.
ncp5215 http://onsemi.com 8 typical operating characteristics figure 2. reference voltage vs. ambient temperature figure 3. switching frequency vs. ambient temperature figure 4. soft ? start current vs. ambient temperature 0.797 0.798 0.799 0.8 0.801 0.802 0.803 ? 40 ? 15 10 35 60 85 v ref , reference voltage (v) t a , ambient temperature ( c) 294 296 298 300 302 304 306 ? 40 ? 15 10 35 60 85 t a , ambient temperature ( c) f sw , switching frequency (khz) 3.7 3.8 3.9 4 4.1 4.2 4.3 ? 40 ? 15 10 35 60 85 i ss , soft ? start current ( a) t a , ambient temperature ( c) 2.3 2.4 2.5 2.6 2.7 2.8 2.9 ? 40 ? 15 10 35 60 8 5 figure 5. v drp gain vs. ambient temperature t a , ambient temperature ( c) gain_cs, vcrp gain (v/v) 2.3 2.4 2.5 2.6 2.7 2.8 2.9 ? 40 ? 15 10 35 60 85 r drp , internal droop resistance (k ) t a , ambient temperature ( c) figure 6. internal droop resistance vs. ambient temperature 3.7 3.8 3.9 4 4.1 4.2 4.3 ? 40 ? 15 10 35 60 8 5 t a , ambient temperature ( c) i tre , treset offset current ( a) figure 7. treset offset current vs. ambient temperature
ncp5215 http://onsemi.com 9 typical operating characteristics 1.38 1.4 1.42 1.44 1.46 1.48 1.5 1.52 1.54 012345678 i o , output current (a) figure 8. output voltage vs. output current (v o = 1.5 v, without avp function) v in = 20 v, ps v in = 12 v, ps v in = 9 v, ps v in = 20 v, fpwm v in = 12 v, fpwm v in = 9 v, fpwm v o , output voltage (v) 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.1 012345678 v in = 20 v, ps v in = 12 v, ps v in = 9 v, ps v in = 20 v, fpwm v in = 12 v, fpwm v in = 9 v, fpwm figure 9. output voltage vs. output current (vo = 1.05 v, without avp function) i o , output current (a) v o , output voltage (v) 1.38 1.4 1.42 1.44 1.46 1.48 1.5 1.52 1.54 012345678 v in = 20 v, ps v in = 12 v, ps v in = 9 v, ps v in = 20 v, fpwm v in = 12 v, fpwm v in = 9 v, fpwm i o , output current (a) v o , output voltage (v) figure 10. output voltage vs. output current (v o = 1.5 v, with avp function) 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.1 012345678 v in = 20 v, ps v in = 12 v, ps v in = 9 v, ps v in = 20 v, fpwm v in = 12 v, fpwm v in = 9 v, fpwm i o , output current (a) v o , output voltage (v) figure 11. output voltage vs. output current (v o = 1.05 v, with avp function) 0 50 100 150 200 250 300 350 400 012345678 v in = 20 v, ps v in = 12 v, ps v in = 9 v, ps v in = 20 v, fpwm v in = 12 v, fpwm v in = 9 v, fpwm i o , output current (a) f sw , switching frequency (khz) figure 12. switching frequency vs. output current (v o = 1.5 v) 0 50 100 150 200 250 300 350 400 012345678 v in = 20 v, ps v in = 12 v, ps v in = 9 v, ps v in = 20 v, fpwm v in = 12 v, fpwm v in = 9 v, fpwm i o , output current (a) f sw , switching frequency (khz) figure 13. switching frequency vs. output current (v o = 1.05 v)
ncp5215 http://onsemi.com 10 typical operating characteristics 0 20 40 60 80 100 0.01 0.1 1 10 efficiency (%) v in = 20 v, ps 20 v, fpwm 9 v, ps 12 v, ps 12 v, fpwm 9 v, fpwm figure 14. efficiency vs. output current (v o = 1.5 v) i o , output current (a) 0 20 40 60 80 100 0.01 0.1 1 10 v in = 20 v, ps 12 v, ps 9 v, ps 20 v, fpwm 12 v, fpwm 9 v, fpwm 20 v, fpwm 12 v, fpwm efficiency (%) i o , output current (a) figure 15. efficiency vs. output current (v o = 1.05 v)
ncp5215 http://onsemi.com 11 typical operating characteristics top: vin, input voltage ripple, (100mv/div) middle: swn1, ch1 switching node voltage, (10v/div) bottom: swn2, ch2 switching node voltage, (10v/div) time: 2 s/div top: swn1, ch1 switching node voltage, (10v/div) middle 1: vo1, ch1 output voltage ripple, (50mv/div) middle 2: swn2, ch2 switching node voltage, (10v/div) bottom: vo2, ch2 output voltage ripple, (50mv/div) time: 2 s/div figure 16. input voltage ripple with interleaved operation (v o 1 = 1.5 v, i o 1 = 4 a, v o 2 = 1.05 v, i o 2 = 6 a) figure 17. output voltage ripple with interleaved operation (v o 1 = 1.5 v, i o 1 = 4 a, v o 2 = 1.05 v, i o 2 = 6 a ) top: en1, ch1 enable signal, (5v/div) middle 1: pgood1, ch1 power good signal, (5v/div) middle 2: swn1, ch1 switching node voltage, (10v/div) bottom: v o 1, ch1 output voltage, (1v/div) time: 200 s/div figure 18. powerup operation (v o 1 = 1.5 v, i o 1 = 4 a) top: en2, ch2 enable signal, (5v/div) middle 1: pgood2, ch2 power good signal, (5v/div) middle 2: swn2, ch2 switching node voltage, (10v/div) bottom: v o 2, ch2 output voltage, (1v/div) time: 200 s/div figure 19. powerup operation (v o 2 = 1.05 v, i o 2 = 6 a) top: en1, ch1 enable signal, (5v/div) middle 1: pgood1, ch1 power good signal, (5v/div) middle 2: swn1, ch1 switching node voltage, (10v/div) bottom: v o 1, ch1 output voltage, (1v/div) time: 5ms/div figure 20. powerdown operation (v o 1 = 1.5 v, i o 1 = 0 a, fpwm) top: en2, ch2 enable signal, (5v/div) middle 1: pgood2, ch2 power good signal, (5v/div) middle 2: swn2, ch2 switching node voltage, (10v/div) bottom: vo2, ch2 output voltage, (1v/div) time: 5ms/div figure 21. powerdown operation (v o 2 = 1.05 v, i o 2 = 0 a, fpwm)
ncp5215 http://onsemi.com 12 typical operating characteristics top: vo1, ch1 output voltage ripple, (50mv/div) middle: io1, ch1 output current, (5a/div) bottom: swn1, ch1 switching node voltage, (10v/div) time: 20 s/div figure 22. load transient response with fpwm operation (v o 1 = 1.5 v, i o 1 = 0 a ? 4 a ? 0 a) top: vo2, ch2 output voltage ripple, (50mv/div) middle: io2, ch2 output current, (5a/div) bottom: swn2, ch2 switching node voltage, (10v/div) time: 20 s/div figure 23. load transient response with fpwm operation (v o 2 = 1.05 v, i o 2 = 0 a ? 6 a ? 0 a) top: vo1, ch1 output voltage ripple, (50mv/div) middle: io1, ch1 output current, (5a/div) bottom: swn1, ch1 switching node voltage, (10v/div) time: 50 s/div figure 24. load transient response with skip ? mode operation (v o 1 = 1.5 v, i o 1 = 0.1 a ? 4 a ? 0.1 a) top: vo2, ch2 output voltage ripple, (50mv/div) middle: io2, ch2 output current, (5a/div) bottom: swn2, ch2 switching node voltage, (10v/div) time: 50 s/div figure 25. load transient response with skip ? mode operation (v o 2 = 1.05 v, i o 2 = 0.1 a ? 6 a ? 0.1 a) top: fpwm#, fpwm# signal, (5v/div) middle 1: vo1, ch1 output voltage ripple, (50mv/div) middle 2: il1, ch1 inductor current, (5a/div) bottom: swn1, ch1 switching node voltage, (10v/div) time: 50 s/div figure 26. on ? line mode ? changing operation (v o 1 = 1.5 v, i o 1 = 0.2 a, fpwm ? skip mode ? fpwm) top: fpwm#, fpwm# signal, (5v/div) middle 1: vo2, ch2 output voltage ripple, (50mv/div) middle 2: il2, ch2 inductor current, (5a/div) bottom: swn2, ch2 switching node voltage, (10v/div) time: 50 s/div figure 27. on ? line mode ? changing operation (v o 2 = 1.05 v, i o 2 = 0.2 a, fpwm ? skip mode ? fpwm)
ncp5215 http://onsemi.com 13 operation description general the ncp5215, a high ? efficiency and fast ? transient ? response dual ? channel buck controller, provides a multifunctional power solution for notebook power system. 180 interleaved operation function between the two channels has capabilities of reducing the common input capacitor requirement and improving noise immunity. adaptive ? voltage ? positioning (avp) control reduces the requirement of output filter capacitors. programmable power ? saving operation ensures high efficiency over entire load range. input feedforward voltage ? mode control is employed to deal with wide input voltage range. transient ? response ? enhancement (tre) control for the both channels enables fast transient response. pwm operation the ncp5215 operates at a pin ? selectable normal operation switching frequency, allowing 200 khz, 300 khz, or 400 khz. as shown in table 1, the connection of the pin fset determines normal operation frequency in continuous ? conduction ? mode (ccm). table 1. switching frequency selection fset pin float vcc gnd fsw (khz) 200 300 400 to speed up transient response and increase sampling rate, an internal high ? frequency clock is employed, which frequency is four times of the selected normal operating frequency. as an instance, if the fset pin is connected to v cc , the normal switching frequency is set to 300 khz. the internal high ? frequency clock is 1.2 mhz. figure 28 shows internal clocks of the ncp5215 in this case. the 1.2mhz high ? frequency clock with 50% duty ? ratio introduced to the two pwm channels. a digital circuitry generates two interleaved 300 khz clocks using the 1.2 mhz clock and output them to the two pwm channels as normal operation clocks in ccm, respectively. forced ? pwm operation (fpwm mode) if the fpwm# pin is pulled low, the ncp5215 works under forced ? pwm operation and thus always in ccm. the two channels always run in selected fixed frequency and 180 interleaved operation. in this mode, the low ? side gate ? drive signal is forced to be the complement of the high ? side gate ? drive signal. this mode allows reverse inductor current, in such a way that it provides more accurate voltage regulation and fast transient response. during soft ? start operation, the ncp5215 automatically runs in fpwm mode regardless of the fpwm# pin? s setting to guarantee smooth powerup. 1.2mhz 300khz 300khz clk1 clk2 1.2mhz 1.2mhz figure 28. internal clocks in the ncp5215 as f sw = 300 khz digital counter & 180 phase shift osc (4*f sw ) pwm1 pwm2 fast response high sampling rate interleaved in ccm light ? load pulse ? skipping operation (skip mode) if the skip mode is enabled by pulling high fpwm# pin, the ncp5215 works in pulse ? skipping enabled operation (ps). in medium and high load range, the converter still runs in ccm, and the switching frequency is fixed as the selected frequency. if both channels run in ccm, they operate interleaved. in light load range, the converter will enter skip mode if negative inductor current appears continuously. in the skip mode, the bottom mosfet will be turned off when the inductor current is going negative. the top mosfet?s on ? time is fixed to around 1.5 times as the on ? time in ccm. the ncp5215 continuously monitors the voltage at fb pin and comparing to the voltage at vdrp pin. when the fb voltage drops below the vdrp voltage, a fixed on ? time will be initiated at the time of the next coming high ? frequency clock edge, which can be either rising edge or falling edge. the minimum off ? time is half high ? frequency cycle. when the load increases and the inductor current becomes continuous, the controller will automatically return to fixed ? frequency operation and be synchronized to the normal operation clock. transient response enhancement (tre) in the skip mode, the operation of the ncp5215 is similar to constant on ? time scheme. the response time of the controller is between half to one cycle of the high ? frequency clock. however, for a conventional trailing ? edge pwm controller in ccm, the fastest response time is one switching cycle in the worst case. to further improve transient response in ccm, a transient
ncp5215 http://onsemi.com 14 response enhancement circuitry is introduced to the ncp5215. in ccm operation, the controller continuously monitors the output voltage (comp) of the error amplifier to detect load transient events. as shown in figure 1, there is a threshold voltage in each channel made in a way that a filtered comp signal pluses an adjustable offset voltage, which is set by an external resistor. once large load transient occurs, the comp signal is possible to exceed the threshold and then tre signal will be high in a short period, which is typically around one normal switching cycle. in this short period, the controller will be running at high frequency and therefore has faster response. after that the controller comes back to normal switching frequency operation. figure 29 shows tre effect on a load transient response. top: vo (50mv/div), middle: transient signal (20v/div), bottom: swn (10v/div), time: (10us/div) (a) tre disabled top: vo (50mv/div), middle: transient signal (20v/div), bottom: swn (10v/div), time: (10us/div) (b) tre enabled figure 29. transient response comparison on tre the internal offset voltage of the tre threshold is set by an external resistor r tre connected from the treset pin to agnd. v th_tre i tre r tre 4 (eq. 1) where i tre is a sourcing current out the treset pin. a recommended value for v th_tre is around 1.5 times of peak ? to ? peak value of the comp signal in ccm operation. the higher v th_tre , the lower sensitivity to load transient. the tre function can be disabled by pulling high the treset pin to v cc or just leaving it float. adaptive voltage positioning (avp) for applications with fast transient currents, adaptive voltage positioning can reduce peak ? to ? peak output voltage deviations due to load transients and allow use of a smaller output filter. adaptive voltage positioning sets output voltage higher than nominal at light loads, and output voltage is allowed limited sag when the load current is applied. upon removal of the load, output voltage returns no higher than the original level, allowing one output transient peak to be canceled over a load stepup and release cycle. figure 30. adaptive voltage positioning +5% x v o v o with avp v o without avp figure 30 shows how avp works. the waveform labeled ?vo without avp? shows output voltage waveform in a converter without avp. on the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. with avp, the peak ? to ? peak excursions are cut around in half. the controller can be configured to adjust the output voltage based on the output current of the converter as shown in figure 31. in order to realize the avp function, a resistor is connected between v ref and v drp . during no ? load conditions, the vdrp pin voltage stays at the same voltage level as the v ref . as the output current increases, the vdrp pin voltage decreases. this causes v out to droop according to a loadline set by the resistor. in the ncp5215, the output current of each channel is sensed differentially. a high gain and low offset ? voltage differential amplifier in each channel allows low ? resistance current ? sensing resistor or low ? dcr inductor to be used to minimize power dissipation. for lossless inductor current sensing as shown in figure 31, the sensing rc network should satisfy r cs c cs l dcr (eq. 2) where dcr is a dc resistance of a inductor, and normally c cs is selected to be around 0.1 f. in high accuracy
ncp5215 http://onsemi.com 15 applications, to compensate measurement error caused by temperature, an additional resistance network including a negative ? temperature ? coefficient (ntc) thermistor can be connected with c cs in parallel. figure 31. programmable avp with lossless inductor current sensing figure 32. figure 32. programmable avp with resistive current sensing the output voltage with avp is v o v o0 i o r ll (eq. 3) where i o is load current, no ? load output voltage v o0 is set by the external resistor divider, that is v o0 1 r fo r fg v ref (eq. 4) r fo is a resistor connected between the output and the fb pin, and r fg is a resistor connected between the fb pin to agnd. the load ? line impedance r ll by the avp function is given by r ll dcr gain_cs r drp_ext r drp_int r drp_ext v o0 v ref (eq. 5) where dcr is dc resistance of the inductor, gain_cs is a gain from [(cs+) ? (cs ? )] to (vdrp ? vref), r drp_int is a internal resistance connected between the output reference and the vdrp pin, r drp_ext is a external resistance connected between the output reference and the vdrp pin. if an additional current sensing resistor (r cs ) is employed to improve accuracy, as shown in figure 32, the load line resistance can be calculated by r ll r cs gain_cs r drp_ext r drp_int r drp_ext v o0 v ref (eq. 6) the avp function can be easily disabled by shorting vdrp pin and vref pin together. control logic the internal control logic is powered by v cc . figure 33 shows a power ? up and powerdown timing diagram for each channel. figure 34 shows a state diagram for each channel. the ncp5215 continuously monitors v cc and v in level with an undervoltage lockout (uvlo) function. if both v cc and v in are in operation range, and output voltage is below 0.3 v, the converter has a soft ? start after enbl signal goes high. the soft ? start time is programmed by an external capacitor c ss connected from the ss pin to agnd, which can be calculated by t ss 0.8 c ss i ss (eq. 7) where i ss is a sourcing current output from the ss pin. when the enbl goes low, or the internal fault latch is set by over current or output undervoltage, the device operates in soft stop and output discharge mode. the output is discharged to gnd through an internal 12 switch connected from the cs ? /vo pin to the pgnd pin, until the output voltage decreases to 0.3 v. also if restart the system when the output voltage is still above 0.3 v, the device will discharge the output voltage to 0.3 v first and then start soft ? start. overcurrent protection (ocp) the ncp5215 protects power system if overcurrent occurs. the current through each channel is continuously monitored with the dif ferential current sense. current limit threshold is related to an external voltage at the i lim pin, which is normally produced by an external resistor divider (r il1 and r il2 ) connected from the v ref pin to agnd. the current ? limit threshold for peak current is set by i lim(peak) 0.2 r il2 v ref r il1 r il2 dcr (eq. 8) or i lim(peak) 0.2 r il2 v ref r il1 r il2 r cs (eq. 9) if inductor current exceeds the current threshold continuously, the top gate drive will be turned off cycle ? by ? cycle. in the meanwhile, an internal fault timer will be triggered to count normal operation clock. after 16 continuous clock pulses, if the fault still exists the part latches off, both the top gate drive and the bottom gate drive
ncp5215 http://onsemi.com 16 are turned off and their outputs are float. the fault remains set until the system has shutdown and re ? applied power or the enable input signal to the regulator controller has toggled states. overvoltage protection (ovp) an ovp circuit monitors the output voltages to prevent from over voltage. ovp limit is typically 117% of the nominal output voltage level. if the output voltage is above this threshold, an ov fault is set, the top gate drive is turned off, and then the bottom gate drive is latched on to discharge the output. the fault remains set until the system has shutdown and re ? applied power or the enable input signal to the regulator controller has toggled states. undervoltage protection (uvp) a uvp circuit monitors the output voltages to detect undervoltage. uvp limit is 68% of the nominal output voltage level. if the output voltage is below this threshold, a uv fault is set. if an ov protection is set before, the bottom gate drive is forced high. if no ov protection set, an internal fault timer will be triggered to count normal operation clock. after 16 continuous clock pulses, if the fault still exists the part latches off, both the top gate drive and the bottom gate drive are turned off and their outputs are float. the fault remains set until the system has shutdown and re ? applied power or the enable input signal to the regulator controller has toggled states. thermal protection the ncp5215 has a thermal shutdown protection to protect the device from overheating when the die temperature exceeds 150 c. once the thermal protection is triggered, the fault state can be ended by re ? applying v cc , v in , or enbl when the temperature drops down below 120 c. vcca vin enbl vo pgood vcca goes above 4.4v to enable the ic pgood goes high enbl goes high. vo is enabled but not actived until vin goes above 3.5v. soft ? start pgood goes low figure 33. powerup and powerdown timing diagram per channel t sft_start completed 32 cycles
ncp5215 http://onsemi.com 17 power up vcc > 4.25v ? & vin > 4.0v ? & enbl= high ? yes vo < 0.3v yes soft start and normal operation vo discharge mode vcc < 4.0v or vin < 3.5v or enbl = low no & no ov tg & bg latch off ocp oc uvp uv ovp ov tg latch off bg latch on vo discharge mode re ? apply vcc or vin or enbl ov figure 34. state diagram per channel
ncp5215 http://onsemi.com 18 cs1+ cs1 ? /vo1 33 34 tg1 swn1 31 32 fb1 inv1 37 38 ilim1 vdrp1 35 36 comp1 treset1 39 40 cs2+ cs2 ? /vo2 18 17 tg2 swn2 20 19 fb2 inv2 14 13 ilim2 vdrp2 16 15 comp2 treset2 12 11 3 4 1 2 7 8 5 6 9 10 28 27 30 29 24 23 26 25 22 21 agnd vref fset vcc en1 en2 pgood1 pgood2 ss1 ss2 bg1 pgnd1 bst1 vccp1 pgnd2 bg2 vin fpwm# vccp2 bst2 5vcc pgnd 220uf pgnd vo1 vin 5vcc vref 2.2uh l1 co1 cs1 3.6k rs1 m1 m3 ntms4705n ntms4705n ntms4705n ntms4705n m2 m4 cin1 10uf cin2 10uf db1 bat54wt1 cb1 0.1uf cpf1 1uf 0.1uf fpwm# ril11 100k rdp1 2k ril12 82k cdp1 47pf r11 10k 750 r13 11k r14 75k r12 220pf c12 68pf c11 1nf c13 390k rt1 1.5v / 5a 20 rif 15nf cif rcf 20 ccf 1uf cref 1uf css1 4.7nf css2 4.7nf pgood1 pgood2 en1 en2 5vcc 220uf*2 pgnd vo2 vref 1.5uh l2 co2 cs2 4.3k rs2 db2 bat54wt1 cb2 0.1uf 0.1uf ril21 100k rdp2 3k ril22 36k cdp2 47pf r21 13k 910 r23 36k r24 200k r22 220pf c22 68pf c21 820pf c23 200k rt2 1.05v/6a pgnd NCP5215MNR2G cpf2 1uf co11 10uf co21 10uf figure 35. typical application schematic diagram
ncp5215 http://onsemi.com 19 table 2. bill of materials for the typical application item pcs part reference description value package part number manufacturer 1 1 ic1 ncp5215 qfn40 NCP5215MNR2G on semiconductor 2 4 m1, m2, m3, m4 power mosfet 30 v, 12 a, single n ? channel so ? 8 so8 ntms4705n on semiconductor 3 2 db1, db2 schottky diode, 30v sc70 bat54wt1g on semiconductor 4 2 cdp1, cdp2 mlcc cap 50v, 5%, char: cog 47pf 0603 ecj1vb1h470j panasonic c1608c0g1h470j tdk 5 2 c11, c22 mlcc cap 50v, 5%, char: cog 68pf 0603 ecj1vb1h680j panasonic c1608c0g1h680j tdk 6 2 c12, c22 mlcc cap 50v, 5%, char: cog 220pf 0603 ecj1vc1h221j panasonic c1608c0g1h221j tdk 7 1 c23 mlcc cap 50v, 5%, char: cog 820pf 0603 ecj1vc1h821j panasonic c1608c0g1h821j tdk 8 1 c13 mlcc cap 50v, 5%, char: cog 1000pf 0603 ecj1vc1h102j panasonic c1608c0g1h102j tdk 9 2 css1, css2 mlcc cap 50v, 10%, char: x7r 4700pf 0603 ecj1vb1h472k panasonic c1608x7r1h472k tdk 10 1 cif mlcc cap 50v, 10%, char: x7r 15nf 0603 ecj1vb1h153k panasonic c1608x7r1h153k tdk 11 4 cb1, cb2, cs1, cs2 mlcc cap 16v, 10%, char: x7r 0.1 f 0603 ecj1vb1c104k panasonic c1608x7r1h104k tdk 12 4 ccf, cpf1, cpf2, cref mlcc cap 25v, 10%, char: x5r 1 f 0805 ecj2fb1e105k panasonic c3216x5r1h105k tdk 13 2 co11, co21 mlcc cap 10v, 20%, char: x7r 10 f 0805 ecj3yb1c106m panasonic c3216x7r1c106m tdk 14 2 cin1, cin2 mlcc cap 25v, 20%, char: x7r 10 f 1812 c4532x7r1e106m tdk 15 3 co1, co2 (x2) sp ? cap/polymer aluminum ca- pacitors, 22 f, 2 v, esr = 12 m 220 f 7343 eefud0d221xr panasonic 16 2 rcf, rif thick film chip resistors, power rating 0.1w, tol: 1% 20 0603 erj3ekf20r0v panasonic 17 1 r13 thick film chip resistors, power rating 0.1w, tol: 1% 750 0603 erj3ekf7500v panasonic 18 1 r23 thick film chip resistors, power rating 0.1w, tol: 1% 910 0603 erj3ekf9100v panasonic 19 1 rdp1 thick film chip resistors, power rating 0.1w, tol: 1% 2k 0603 erj3ekf2001v panasonic 20 1 rdp2 thick film chip resistors, power rating 0.1w, tol: 1% 3k 0603 erj3ekf3001v panasonic 21 1 rs1 thick film chip resistors, power rating 0.1w, tol: 1% 3.6k 0603 erj3ekf3601v panasonic 22 1 rs2 thick film chip resistors, power rating 0.1w, tol: 1% 4.3k 0603 erj3ekf4301v panasonic 23 1 r11 thick film chip resistors, power rating 0.1w, tol: 1% 10k 0603 erj3ekf1002v panasonic
ncp5215 http://onsemi.com 20 item manufacturer part number package value description part reference pcs 24 1 r14 thick film chip resistors, power rating 0.1w, tol: 1% 11k 0603 erj3ekf1102v panasonic 25 1 r21 thick film chip resistors, power rating 0.1w, tol: 1% 13k 0603 erj3ekf1302v panasonic 26 2 r24, ril22 thick film chip resistors, power rating 0.1w, tol: 1% 36k 0603 erj3ekf3602v panasonic 27 1 r12 thick film chip resistors, power rating 0.1w, tol: 1% 75k 0603 erj3ekf7502v panasonic 28 1 ril12 thick film chip resistors, power rating 0.1w, tol: 1% 82k 0603 erj3ekf8202v panasonic 29 2 ril11, ril21 thick film chip resistors, power rating 0.1w, tol: 1% 100k 0603 erj3ekf1003v panasonic 30 2 r22, rt2 thick film chip resistors, power rating 0.1w, tol: 1% 200k 0603 erj3ekf2003v panasonic 31 1 rt1 thick film chip resistors, power rating 0.1w, tol: 1% 390k 0603 erj3ekf3903v panasonic 32 1 l1 power choke coil, dcr = 7.0m , idc = 12a, isat = 27a 2.2 h pcmc104t ? 2r2mn cyntec 33 1 l2 power choke coil, dcr = 4.2m , idc = 16a, isat = 33a 1.5 h pcmc104t ? 1r5mn cyntec
ncp5215 http://onsemi.com 21 package dimensions qfn40 6x6, 0.5p mn suffix case 488ar ? 01 issue a seating 40x k 0.15 c (a3) a a1 d2 b 1 11 20 21 40 2x 2x e2 40x 10 30 40x l 40x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 31 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 4.00 4.20 e 6.00 bsc 4.20 e2 4.00 e 0.50 bsc l 0.30 0.50 k 0.20 ??? 36x plane dimensions: millimeters 0.50 pitch 4.20 0.30 4.20 40x 36x 0.65 40x 6.30 6.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp5215/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca sales representative

▲Up To Search▲

Price & Availability of NCP5215MNR2G

	To Download NCP5215MNR2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .